Low-consumption switched-capacitor circuit

ABSTRACT

A switched-capacitor circuit including at least one first capacitor and a circuit for switching at least one armature of the first capacitor alternately to one and the other of two terminals at a switching frequency. The circuit further includes a second capacitor connected to the first capacitor at a node; and a filtering circuit connecting the node to a virtual ground only for frequencies belonging to a frequency range.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to switched-capacitor circuits and morespecifically to switched-capacitor circuits of very high resolution.

2. Discussion of the Related Art

A switched-capacitor circuit comprises at least one capacitor having atleast one armature alternately connected, at a switching frequency, toone or the other of two terminals by switches. In operation, theassembly formed by the capacitor and the associated switches has anequivalent resistance equal to the ratio of the switching period to thecapacitance of the capacitor. Switched-capacitor circuits have manyadvantages. They enable to simulate a variable resistance which dependson the switching frequency. This is the reason why switched-capacitorcircuits are especially used for the forming of filters having a cut-offfrequency depending on the switching frequency. Further, for equivalentmanufacturing technologies, a switched-capacitor circuit takes up asmaller surface area when integrated than that which would be taken upby an equivalent circuit formed with real resistors. Further, forequivalent manufacturing technologies, the capacitance of an integratedcapacitor may be obtained with an accuracy greater than that of aresistor.

The current tendency is to form switched-capacitor circuits of very highresolution, that is, for which the signal-to-noise ratio or SNR isgreater than some hundred decibels. For a conventionalswitched-capacitor circuit, this requires increasing the capacitances ofthe circuit capacitors up to values that can exceed several hundreds ofpicofarads. The capacitance increase of the capacitors translates as anunwanted increase of the total consumption of the switched-capacitorcircuit. It is further generally difficult to integrate capacitors withhigh capacitances.

SUMMARY OF THE INVENTION

The present invention aims at a switched-capacitor circuit enabling toobtain a high SNR while maintaining a low consumption.

Another object of the present invention is the forming of aswitched-capacitor circuit taking up a decreased surface area when it ismade in integrated form.

For this purpose, the present invention provides a switched-capacitorcircuit comprising at least one first capacitor and a circuit forswitching at least one armature of the first capacitor alternately toone or the other of two terminals at a switching frequency. The circuitfurther comprises a second capacitor connected to the first capacitor ata node and a filtering circuit connecting the node to a virtual groundonly for frequencies belonging to a frequency range.

According to an embodiment, the filtering circuit is capable ofconnecting the node to the virtual ground only for frequencies smallerthan a threshold frequency greater than half the switching frequency.

According to an embodiment, the filtering circuit comprises an amplifierwith differential inputs having an input connected to the node andhaving a main cut-off frequency, the threshold frequency of thefiltering circuit corresponding to the main cut-off frequency.

According to an embodiment, the filtering circuit comprises at least oneactive filter comprising at least one active electronic component and atleast one passive filter comprising at least one passive electroniccomponent.

According to an embodiment, the capacitance of the second capacitor issmaller than the capacitance of the first capacitor.

According to an embodiment, the first capacitor comprises first andsecond armatures, the circuit comprising first, second, and thirdterminals; a first switch connecting the first terminal to the firstarmature of the first capacitor; a second switch connecting the secondterminal to the first armature of the first capacitor; a third switchconnecting the third terminal to the second armature of the firstcapacitor; and a fourth switch connecting the node to the secondarmature of the first capacitor, the first and fourth switches beingcontrolled by a first binary signal and the second and third switchesbeing controlled by a second binary signal, the first and second binarysignals being non-overlapping.

According to an embodiment, the filtering circuit comprises anoperational amplifier comprising an input connected to said node and anoutput connected to said input via the second capacitor, the thresholdfrequency of the filtering circuit corresponding to the cut-offfrequency of the operational amplifier.

According to an embodiment, the second terminal is connected to a sourceof the reference voltage and the operational amplifier comprises anadditional input connected to said source of the reference voltage.

According to an embodiment, the circuit further comprises a fifth switchacross the second capacitor, the fifth switch being on, when the firstand fourth switches are on, for a first time period and off for a secondtime period.

According to an embodiment, the circuit further comprises a thirdcapacitor comprising third and fourth armatures, the operationalamplifier comprising an additional input connected to an additional nodeand an additional output connected to the additional input via a fourthcapacitor; fourth and fifth terminals; a sixth switch controlled by thefirst signal connecting the fourth terminal to the third armature of thethird capacitor; a seventh switch controlled by the second signalconnecting the fifth terminal to the fourth armature of the thirdcapacitor; and an eighth switch controlled by the first signalconnecting the additional node to the fourth armature of the thirdcapacitor, the second terminal being located between the third armatureof the third capacitor and the fifth switch.

The foregoing objects, features, and advantages of the present inventionwill be discussed in detail in the following non-limiting description ofspecific embodiments in connection with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 schematically shows a conventional embodiment of aswitched-capacitor circuit;

FIG. 2 shows an electric circuit used to model the noise transferfunction of the circuit of FIG. 1;

FIG. 3 schematically shows the variation of the noise power spectraldensity at the output of the circuit of FIG. 2;

FIGS. 4 and 5 are drawings respectively similar to FIGS. 1 and 2 of avariation of the circuit of FIG. 1;

FIG. 6 shows an electric circuit illustrating the operating principle ofa switched-capacitor circuit according to the present invention;

FIG. 7 shows an embodiment of a switched-capacitor circuit according tothe present invention;

FIG. 8 schematically shows the variation of the noise power spectraldensity at the output of the circuit of FIG. 7;

FIG. 9 shows an alternative embodiment of the circuit of FIG. 7;

FIGS. 10 and 12 show two conventional embodiments of an integrator withswitched capacitors; and

FIGS. 11 and 13 show two embodiments of an integrator with switchedcapacitors according to the present invention.

DETAILED DESCRIPTION

For clarity, the same elements have been designated with the samereference numerals in the different drawings. Further, in the followingdescription, the same reference is used to designate a capacitiveelement, or capacitor, and its capacitance, and the same reference isused to designate a resistive element, or resistor, and the value of itsresistance. Further, “switched-capacitor circuit” is used in a generalsense and may designate a circuit comprising a single capacitor havingat least one of its armatures switched between two terminals.

FIG. 1 shows a conventional example of a switched-capacitor circuit 10comprising an input terminal IN and an output terminal OUT. Call V_(IN)the voltage between terminal IN and a source of a reference voltage, forexample, ground GND, and V_(OUT) the voltage between terminal OUT andground GND. Circuit 10 comprises a capacitor C₀ having an armatureconnected to a node A and its other armature connected to a node B. NodeA is connected to terminal IN via a switch SW₁ controlled by a controlsignal P₁. Node A is further connected to ground GND via a switch SW₂controlled by a control signal P₂. Node B is connected to terminal OUTvia a switch SW₃ controlled by signal P₂. Node B is further connected toground GND via a switch SW₄ controlled by signal P₁. As an example,control signals P₁ and P₂ are binary signals alternating between a highstate, noted “1”, and a low state, noted “0”. As an example, when signalP₁ is at “1” (signal P₂ at “0”), switches SW₁ and SW₄ are on andswitches SW₂ and SW₃ are off. When signal P₁ is at “0” (signal P₂ at“1”), switches SW₁ and SW₄ are off and switches SW₂ and SW₃ are on.Signals P₁ and P₂ are non-overlapping, that is, they are notsimultaneously in the state for which they control the turning-on of theassociated switch (the high state in the present example). However,signals P₁ and P₂ may be simultaneously in the state for which theycontrol the turning-off of the associated switches (the low state in thepresent example). As an example, signals P₁ and P₂ are complementary,that is, signal P₁ is in the low state when signal P₂ is in the highstate and conversely. As an example, signals P₁ and P₂ are periodic witha frequency f_(S) (called switching frequency or sampling frequencyhereafter) and a period T_(S). Call α the duty cycle of signal P₁. Thismeans that over a time period T_(S), signal P₁ is in the high state forduration αT_(S) and in the low state for duration (α−1)T_(S), α beingstrictly smaller than 1. As an example, α is equal to ½.

Conventionally, circuit 10 is equivalent to a resistor R placed betweenterminals IN and OUT and having a resistance equal to:R=T _(S) /C ₀=1/(C ₀ f _(S))  (1)

FIG. 2 shows a circuit 12 equivalent to the circuit 10 used to estimatethe noise power spectral density at the output of circuit 10. In thecase where switches SW₁ and SW₄ are formed of MOS transistors, it can beconsidered that, when switches SW₁ and SW₄ are on, circuit 10 isequivalent to a source S_(b) of a thermal noise in series with aresistor R_(ON) which corresponds to the internal resistance of MOStransistors in the on state. Voltage V_(IN) provided by noise sourceS_(b) is filtered by a low-pass filter formed by resistor R_(ON) andcapacitor C₀ and having the following transfer function H:

$\begin{matrix}{H = \frac{1}{1 + {j\frac{f}{f_{C}}}}} & (2)\end{matrix}$where f_(C) is the cut-off frequency of the low-pass filter and is equalto:f _(C)=1/2πR _(ON) C ₀  (3)

It is considered that cut-off frequency f_(C) is much higher thansampling frequency f_(S), to obtain a proper charge of capacitor C₀.

The spectral power density S₀ of the noise provided by source S_(b) isequal to:S ₀=4kTR _(ON)  (4)where k is Boltzmann's constant and T is temperature.

The noise power spectral density S₁ at the output of circuit 12 is equalto:

$\begin{matrix}{S_{1} = \frac{S_{0}}{1 + \left( \frac{f}{f_{C}} \right)^{2}}} & (5)\end{matrix}$

FIG. 3 schematically shows the variation of noise spectral density S₁.After sampling at frequency f_(S), noise power spectral density S₂ atthe output of circuit 10 is provided by the following relation:

$\begin{matrix}{{S_{2}(f)} = {S_{0}{\sum\limits_{n = {- \infty}}^{n = {+ \infty}}\;\frac{1}{1 + \left( \frac{f - {nf}_{S}}{f_{C}} \right)^{2}}}}} & (6)\end{matrix}$

Call f_(N)/2 the maximum frequency of the useful signal to betransmitted. To respect Shannon's sampling criterion, frequency f_(N)/2must be smaller than half sampling frequency f_(S). Relation (6) showsan aliasing in the useful band of the thermal noise due to thesub-sampling of the wide-band noise.

In practice, frequency f_(N) is much smaller than sampling frequencyf_(S). As an example, frequency f_(S) is on the order of 1 MHz andfrequency f_(N) is on the order of 1 kHz. An approached value of the RMSvalue of the noise voltage at the output of circuit V_(b) can bedetermined in a simple way. First, the sampling is not taken intoaccount. The RMS value of noise voltage V_(b) at the output of circuit12 is provided by the following relation:

$\begin{matrix}{V_{b} = {\sqrt{\int_{0}^{+ \infty}{{S_{1}(f)}\ {\mathbb{d}f}}} = {\sqrt{S_{0}{\int_{0}^{+ \infty}{\frac{1}{1 + \left( \frac{f}{f_{C}} \right)^{2}}{\mathbb{d}f}}}}\mspace{25mu} = {\sqrt{S_{0}f_{C}\frac{\pi}{2}}\mspace{25mu} = \sqrt{\frac{kT}{C_{0}}}}}}} & (7)\end{matrix}$

The noise being sampled at frequency f_(S), the noise is taken back intofrequency band [0,f_(S)/2]. Further, the useful signal being infrequency band [0,f_(N)/2], only part of the noise is kept. The RMSvalue of the aliased noise voltage corresponds to:

$\begin{matrix}{V_{b} = \sqrt{\frac{kT}{C_{0}\frac{f_{S}}{f_{C}}}}} & (8)\end{matrix}$

A possibility to decrease the RMS value of noise voltage V_(b) is toincrease capacitance C₀. Typically, to obtain an SNR greater than somehundred decibels, capacitance C₀ must be greater than some hundredpicofarads. A disadvantage is that circuit 10 generally belongs to acircuit comprising other capacitors having values depending on C₀. Forexample, circuit 10 may belong to an integrator, possibly comprisinganother capacitor, called integration capacitor, having a capacitancethat can be equal to approximately 10 times C₀. The integrated formingof capacitors having high capacitances, for example, greater thanseveral hundreds of picofards, is difficult. Further, the increase inthe capacitances of the capacitors of switched-capacitor circuitsresults in an increase in the total circuit consumption. This may beincompatible with applications for which the total circuit consumptionis critical.

To increase the SNR of a switched-capacitor circuit without increasingthe capacitance of the circuit capacitor, the applicant has firstattempted to replace capacitor C₀ with two series-assembled capacitorsto form a capacitive bridge.

FIG. 4 shows a switched-capacitor circuit 14 having a structure similarto that of circuit 10 of FIG. 1, with the difference that capacitor C₀has been replaced with a capacitor C₁ and that a capacitor C₂ has beenadded between switch SW₄ and ground GND. Capacitance C₁ is greater thancapacitance C₂. As an example, capacitance C₁ may be equal to ten timescapacitance C₂. A node located between switch SW₄ and capacitor C₂ isdesignated as N.

FIG. 5 is an electric diagram 16 equivalent to circuit 14 when switchesSW₁ and SW₄ are on and which illustrates the operation thereof. VoltageV_(OUT) corresponds to the voltage across capacitor C₁. Call V′_(OUT)the voltage between node A and ground GND.

Transfer function H′ of circuit 16 is:

$\begin{matrix}{{H^{\prime}(f)} = {\frac{V_{OUT}}{V_{IN}} = {{\frac{V_{OUT}}{V_{OUT}^{\prime}}\frac{V_{OUT}^{\prime}}{V_{IN}}} = {\frac{C_{2}}{C_{2} + C_{1}}\frac{1}{1 + {j\frac{f}{f_{C}^{\prime}}}}}}}} & (9)\end{matrix}$where f′_(C) is the cut-off frequency of the low-pass filter formed byresistor R_(ON) and capacitors C₁ and C₂. At low frequencies, transferfunction H′ of circuit 16 is substantially equal to transfer function Hof circuit 12 multiplied by attenuation factor C₂/(C₁+C₂). Whencapacitance C₁ is equal to 10 times capacitance C₂, the attenuationfactor is 1/11. The capacitive bridge formed by capacitors C₁ and C₂thus enables to decrease the contribution of noise across capacitor C₁.A 21-dB gain on the noise is thus obtained. However, the amplitude ofthe useful signal at low frequencies is also decreased by 21 decibels.The SNR of circuit 16 is thus not improved with respect to that ofcircuit 12.

The applicant has demonstrated that all of the useful low-frequencysignal and only part of the high-frequency noise across capacitor C₁could be obtained by connecting node N between capacitors C₁ and C₂ to a“virtual low-frequency ground”.

FIG. 6 shows a circuit 20 illustrating the principle of a virtuallow-frequency ground. Node N is connected to a virtual low-frequencyground GND′ by a line 22 shown in dotted lines. Capacitor C₂, on theside opposite to node N, is connected to a circuit S_(C). For lowfrequencies, virtual ground GND′ is equivalent to ground GND. Everythinghappens as if node N was then directly connected to ground GND,short-circuiting capacitor C₂. For high frequencies, everything happensas if ground GND′ was not present and as if node B was normallyconnected to capacitor C₂. At high frequencies, circuit S_(C) maintainsthe armature of capacitor C₂ at a fixed voltage. The low-frequencycomponents and especially the useful signal are thus only seen bycapacitor C₁ while the high-frequency components (and, in particular,the high-frequency components of the wide-band thermal noise) are sharedbetween capacitors C₁ and C₂. Advantage is thus taken of the attenuationof the high-frequency components of the noise without for the usefulsignal to be attenuated. Thereby, at the aliasing of the spectrum due tothe sampling, the contribution of the high-frequency noise in the usefulfrequency band is decreased. Thereby, to obtain a given SNR, capacitanceC₁ of circuit 20 according to the present invention may be smaller, forexample, up to ten times, than capacitance C₀ of conventional circuit10. The capacitances of capacitors C₁ and C₂ being low, the integratedmanufacturing of circuit 20 is eased and the consumption of circuit 20is decreased.

According to an embodiment the virtual “low frequency” ground is formedby a differential-input amplifier having an input connected to node Nand having its other input connected to ground GND. Call main cut-offfrequency the lowest frequency for which the amplifier gain falls by 3dB with respect to the maximum amplifier gain. The amplifier maycomprise active components (for example, an operational amplifier) andpossibly passive components (resistor, capacitor, etc.).

FIG. 7 shows an embodiment of a switched-capacitor circuit 30 with avirtual ground. Circuit 30 comprises all the elements of circuit 14 ofFIG. 4, but node N is connected to an inverting input I− of anoperational amplifier 32. Non-inverting input I+ of operationalamplifier 32 is connected to ground GND. Capacitor C₂ is providedbetween node N and output O+ of operational amplifier 32.Conventionally, operational amplifier 32 has a cut-off frequency f′_(C)on the order of from 1 to a few Megahertz, for example, 2 MHz, which issmaller than cut-off frequency f_(C) and is greater than half switchingfrequency f_(S) of switches SW₁ to SW₄. In the following description,frequencies smaller than cut-off frequency f′_(C) are called lowfrequencies and frequencies greater than cut-off frequency f′_(C) arecalled high frequencies

The operation of circuit 30 will be described when switches SW₁ and SW₄are on. For frequencies smaller than cut-off frequency f′_(C),operational amplifier 32 operates normally. In particular, the voltagesat inverting and non-inverting inputs I− and I+ of operational amplifier32 are equal. Node N is thus effectively directly connected to groundGND. For frequencies greater than cut-off frequency f′_(C), operationalamplifier 32 no longer operates properly, and everything happens as ifit was not present, with output O+ being at high impedance. Thehigh-frequency components are thus well distributed between capacitorsC₁ and C₂.

FIG. 8 schematically shows an example of the variation of the noisepower spectral density S₃ at the output of circuit 30 without taking thesampling into account. At low frequencies, the 1/f noise contribution ofoperational amplifier 32, also called flicker noise, can be observed.The amplitude of noise power spectral density S₃ at the output ofcircuit 30 decreases for frequencies greater than f′_(C). In thesampling, the high-frequency components of the thermal noise are aliasedon interval [0, f_(S)/2]. Due to the fact that these high-frequencycomponents have been attenuated, their contribution in useful band [0,f_(N)/2] is decreased.

Capacitance C₂ should advantageously be as low as possible with respectto C₁ to improve the attenuation of the high-frequency components.However, when switches SW₁ and SW₄ are on, voltage V_(S) at output O+ ofthe amplifier is equal to:

$\begin{matrix}{V_{S} = {{- \frac{C_{1}}{C_{2}}}V_{IN}}} & (10)\end{matrix}$so that if the ratio of capacitances C₁ and C₂ is too high, operationalamplifier 32 risks saturating.

FIG. 9 shows a switched-capacitor circuit 35 corresponding to avariation of circuit 30 of FIG. 7 in which a switch SW₅ is arrangedacross capacitor C₂. Switch SW₅ is controlled by a control signal P₃.During time αT_(S) for which signal P₁ is in the high state, signal P₃is in the low state (switch SW₅ off) for a time period βαT_(S), β beingstrictly smaller than 1, and then in the high state (switch SW₅ off) fortime period (1−β)αT_(S). During time period (1−α)T_(S) for which signalP₁ is in the low state, signal P₃ is in the high state (switch SW₅ off).Value β is selected so that capacitor C₂ does not have time tocompletely charge during time period βαT_(S) so that voltage V_(S) doesnot reach too high values, likely to cause the saturation of operationalamplifier 32. For a conventional operational amplifier 32, and for aratio C₁/C₂ equal to 10, β may be on the order of 1/2.

FIG. 10 shows a conventional example of application ofswitched-capacitor circuit 10 of FIG. 1 for the forming of an integrator40. Terminal OUT of circuit 10 is connected to inverting input I′− of anoperational amplifier 42. Non-inverting input I′+ of operationalamplifier 42 is connected to ground GND. A capacitor C₃ is providedbetween inverting input I′− and an output terminal OUT′ of integrator40. Output O′+ of operational amplifier 42 is connected to terminalOUT′.

The operation of integrator 40 will now be schematically described,assuming that voltage V_(OUT)′ is initially equal to V₀ and consideringthat signal P₁ is in the low state (signal P₂ in the high state).Switches SW₁ and SW₄ are then off and switches SW₂ and SW₃ are on. Thecharge stored in the right-hand armature of capacitor C₀ shown to theright of FIG. 10 is zero and the charge stored in the armature ofcapacitor C₃ shown to the left of FIG. 10 is equal to −C₃V₀.

When signal P₁ switches to the high state (P₂ in the low state), whichcorresponds to an accumulation phase, switches SW₁ and SW₄ are on andswitches SW₂ and SW₃ are off. Capacitors C₀ and C₃ are separate. Charge−C₃V₀ remains trapped on the left-hand armature of capacitor C₃. Thevoltage at terminal OUT′ does not change. Further, capacitor C₀ chargesand the right-hand armature of capacitor C₀ receives charge −C₀V_(IN).

When signal P₁ switches back to the low state (P₂ in the high state),which corresponds to an integration phase, capacitors C₀ and C₃ areconnected to each other again. The output voltage of amplifier 42 thenswitches to V′_(OUT). The balance of the charges between capacitors C₀and C₃ can be written as:0−C ₃ V′ _(OUT) =−C ₀ V _(IN) −C ₃ V ₀  (11)that is:V′ _(OUT) =V ₀+(C ₀ /C ₃)V _(IN)  (12)

At each switching cycle of switches SW₁ to SW₄, voltage V′_(OUT) isequal to the sum of the value of the preceding cycle and of a termproportional to V_(IN). An integrator operation is thus obtained.

FIG. 11 shows an embodiment of an integrator 50 of the type shown inFIG. 10, implementing circuit 30 shown in FIG. 9. For this purpose,output terminal OUT of circuit 30 is connected to inverting input I′− ofoperational amplifier 42.

The operation of circuit 50 will now be described. When signal P₁ is inthe high state during time αT_(S), that is, during the acquisitionphase, switches SW₁ and SW₄ are on and switches SW₂ and SW₃ are off.Circuit 30 is not connected to operational amplifier 42 and operates asdescribed previously. More specifically, switch SW₅ is off during timeβαT_(S) and is on during time (1−β)αT_(S).

When signal P₁ is in the low state for time (1−α)T_(S), that is, duringthe integration phase, switches SW₁ and SW₄ are off and switches SW₂,SW₅, and SW₃ are on. Node B is no longer connected to node N andcapacitor C₁ is connected to operational amplifier 42 identically towhat has been previously described for capacitor C₀ of circuit 40. Thehigh-frequency noise components which might be present during theintegration phase are filtered by operational amplifier 42.

FIG. 12 shows a conventional embodiment of an integrator 60 having adifferential structure. Integrator 60 comprises the elements of circuit40 and, further, a capacitor C′₁ having an armature connected to aninput terminal IN′ by a switch SW′₁ and is connected to switch SW₂. Theother armature of capacitor C′₁ is connected to non-inverting input I′+of differential amplifier 32 via a switch SW′₃ and to switch SW₄. SwitchSW′₁ is controlled by signal P₁ and switch SW′₃ is controlled by switchP₂. Inverting input I′− of operational amplifier 42 is connected to anoutput terminal OUT″. A capacitor C′₃ is provided between non-invertinginput I′+ and inverting output O′− of operational amplifier 42. Theoperation of integrator 60 is identical to that of integrator 40, therole of ground GND for integrator 40 being played, in this case, by thecommon-mode voltage of operational amplifier 42.

FIG. 13 shows the use of circuit 30 according to the present inventionarranged in differential form for the forming of a positive differentialintegrator 70. Integrator 70 comprises the elements of circuit 60 and,further, a switch SW′₄ connecting capacitor C′₁ to non-inverting inputI+ of operational amplifier 32. Integrator 70 further comprises acapacitor C′₂ arranged between non-inverting input I+ and invertingoutput O− of operational amplifier 32 and a switch SW′₅ arranged acrosscapacitor C′₂. Switch SW′₅ is controlled by signal P₃. The operation ofintegrator 70 is identical to that of integrator 50, the role of groundGND for integrator 40 being played, in this case, by the common-modevoltage of operational amplifier 42.

The present invention enables to decrease the contribution of thehigh-frequency noise in the frequency band of the useful signal.Thereby, for a same SNR, it enables to decrease capacitance C₁ ofcircuit 30, 35 with respect to capacitance C₀ of circuit 10. In thepresent embodiment, capacitance C₁ may be ten times smaller thancapacitance C₀. Further, when the switched-capacitor circuit is used toform an integrator, integration capacitance C₃ may be advantageouslydecreased with respect to a conventional circuit, for example, by afactor 10. More generally, the use of the switched-capacitor circuitaccording to the present invention in an electronic system may enable todecrease the capacitances of other capacitors of the electronic system.The present invention advantageously enables to decrease the surfacearea necessary to make switched-capacitor circuit 40 in integrated form,the surface area taken up by operational amplifier 32 beingsubstantially equivalent to the surface area taken up by a capacitorhaving a capacitance of a few picofarads.

The present invention further provides a consumption gain on the orderof from 7 to 8 with respect to a conventional switched-capacitorcircuit. The circuit consumption is not exactly decreased by capacitanceratio C₁/C₂ since the consumption of operational amplifier 32 must betaken into account. Further, when the switched-capacitor circuitcorresponds to a stage of an electronic system comprising severalsuccessive stages, the decrease in the input capacitance of theswitched-capacitor circuit enables to decrease the constraints on thestage preceding the switched-capacitor circuit, for example, apre-amplifier.

Specific embodiments of the present invention have been described.Different variations and modifications will occur to those skilled inthe art. In particular, although an example of a switched-capacitorcircuit comprising four switches SW₁ to SW₄ has been described, itshould be clear that the present invention can apply to aswitched-capacitor circuit in which a same armature of capacitor C₁ isswitched between terminals IN and OUT, the other armature of capacitorC₁ being then connected to inverting input I− of operational amplifier32.

Such alterations, modifications, and improvements are intended to bepart of this disclosure, and are intended to be within the spirit andthe scope of the present invention. Accordingly, the foregoingdescription is by way of example only and is not intended to belimiting. The present invention is limited only as defined in thefollowing claims and the equivalents thereto.

1. A switched-capacitor circuit comprising: input, ground and outputterminals; a first capacitor comprising first and second armatures; asecond capacitor connected to the second armature of the first capacitorat a node; a first switch connecting the input terminal to the firstarmature of the first capacitor, wherein the first switch is responsiveto a first signal at a switching frequency; a second switch connectingthe ground terminal to the first armature of the first capacitor,wherein the second switch is responsive to a second signal at theswitching frequency, the second signal being different from the firstsignal, and the first and second signals having non-overlapping phases;a third switch directly connecting the second armature of the firstcapacitor to the output terminal; a filtering circuit connecting saidnode to a virtual ground only during first phases of the first signal,these first phases being the phases of signal storage of said input inthe first capacitor; and a fourth switch connecting the node to thesecond armature of the first capacitor, the first and fourth switchesbeing controlled by the first signal and the second and third switchesbeing controlled by the second signal, wherein the first and secondsignals are binary signals.
 2. The circuit of claim 1, wherein thefiltering circuit is adapted for connecting the node to the virtualground only for frequencies smaller than a threshold frequency greaterthan half the switching frequency.
 3. The circuit of claim 2, whereinthe filtering circuit comprises an amplifier with differential inputshaving an input connected to the node and having a main cut-offfrequency, the threshold frequency of the filtering circuitcorresponding to the main cut-off frequency.
 4. The circuit of claim 1,wherein the filtering circuit comprises at least one active filtercomprising at least one active electronic component and at least onepassive filter comprising at least one passive electronic component. 5.The circuit of claim 1, wherein the capacitance of the second capacitoris smaller than the capacitance of the first capacitor.
 6. The circuitof claim 1, wherein the filtering circuit comprises an operationalamplifier comprising an input connected to said node and an outputconnected to said input via the second capacitor, wherein a thresholdfrequency of the filtering circuit corresponds to a cut-off frequency ofthe operational amplifier.
 7. The circuit of claim 6, wherein the groundterminal is connected to a source of a reference voltage and wherein theoperational amplifier comprises an additional input connected to saidsource of the reference voltage.
 8. The circuit of claim 1, furthercomprising a fifth switch across the second capacitor, the fifth switchbeing on, when the first and fourth switches are on, for a first timeperiod and off for a second time period.
 9. The circuit of claim 6,further comprising: a third capacitor comprising third and fourtharmatures, the operational amplifier comprising an additional inputconnected to an additional node and an additional output connected tothe additional input via a fourth capacitor; fourth and fifth terminals;a sixth switch controlled by the first signal connecting the fourthterminal to the third armature of the third capacitor; a seventh switchcontrolled by the second signal connecting the fifth terminal to thefourth armature of the third capacitor; and an eighth switch controlledby the first signal connecting the additional node to the fourtharmature of the third capacitor, the second terminal being locatedbetween the third armature of the third capacitor and the fifth switch.10. A switched-capacitor circuit comprising: input, ground and outputterminals; a first capacitor comprising first and second armatures; asecond capacitor connected to the second armature of the first capacitorat a node; a first switch connecting the input terminal to the firstarmature of the first capacitor, wherein the first switch is responsiveto a first signal at a switching frequency; a second switch connectingthe ground terminal to the first armature of the first capacitor,wherein the second switch is responsive to a second signal at theswitching frequency, the second signal being different from the firstsignal, and the first and second signals having non-overlapping phases;a third switch directly connecting the second armature of the firstcapacitor to the output terminal; a filtering circuit connecting saidnode to a virtual ground only during first phases of the first signal,these first phases being the phases of signal storage of said input inthe first capacitor, wherein the filtering circuit comprises anoperational amplifier comprising an input connected to said node and anoutput connected to said input via the second capacitor, wherein athreshold frequency of the filtering circuit corresponds to a cut-offfrequency of the operational amplifier; and a fifth switch across thesecond capacitor, the fifth switch being on, when the first and fourthswitches are on, for a first time period and off for a second timeperiod.
 11. The circuit of claim 10, wherein the filtering circuit isadapted for connecting the node to the virtual ground only forfrequencies smaller than a threshold frequency greater than half theswitching frequency.
 12. The circuit of claim 11, wherein the filteringcircuit comprises an amplifier with differential inputs having an inputconnected to the node and having a main cut-off frequency, the thresholdfrequency of the filtering circuit corresponding to the main cut-offfrequency.
 13. The circuit of claim 10, wherein the filtering circuitcomprises at least one active filter comprising at least one activeelectronic component and at least one passive filter comprising at leastone passive electronic component.
 14. The circuit of claim 10, whereinthe capacitance of the second capacitor is smaller than the capacitanceof the first capacitor.
 15. The circuit of claim 10, wherein the groundterminal is connected to a source of a reference voltage and wherein theoperational amplifier comprises an additional input connected to saidsource of the reference voltage.
 16. The circuit of claim 10, furthercomprising: a third capacitor comprising third and fourth armatures, theoperational amplifier comprising an additional input connected to anadditional node and an additional output connected to the additionalinput via a fourth capacitor; fourth and fifth terminals; a sixth switchcontrolled by the first signal connecting the fourth terminal to thethird armature of the third capacitor; a seventh switch controlled bythe second signal connecting the fifth terminal to the fourth armatureof the third capacitor; and an eighth switch controlled by the firstsignal connecting the additional node to the fourth armature of thethird capacitor, the second terminal being located between the thirdarmature of the third capacitor and the fifth switch.
 17. Aswitched-capacitor circuit comprising: input, ground and outputterminals; a first capacitor comprising first and second armatures; asecond capacitor connected to the second armature of the first capacitorat a node; a first switch connecting the input terminal to the firstarmature of the first capacitor, wherein the first switch is responsiveto a first signal at a switching frequency; a second switch connectingthe ground terminal to the first armature of the first capacitor,wherein the second switch is responsive to a second signal at theswitching frequency, the second signal being different from the firstsignal, and the first and second signals having non-overlapping phases;a third switch directly connecting the second armature of the firstcapacitor to the output terminal; a filtering circuit connecting saidnode to a virtual ground only during first phases of the first signal,these first phases being the phases of signal storage of said input inthe first capacitor, wherein the filtering circuit comprises anoperational amplifier comprising an input connected to said node and anoutput connected to said input via the second capacitor, wherein athreshold frequency of the filtering circuit corresponds to a cut-offfrequency of the operational amplifier; a third capacitor comprisingthird and fourth armatures, the operational amplifier comprising anadditional input connected to an additional node and an additionaloutput connected to the additional input via a fourth capacitor; fourthand fifth terminals; a sixth switch controlled by the first signalconnecting the fourth terminal to the third armature of the thirdcapacitor; a seventh switch controlled by the second signal connectingthe fifth terminal to the fourth armature of the third capacitor; and aneighth switch controlled by the first signal connecting the additionalnode to the fourth armature of the third capacitor, the second terminalbeing located between the third armature of the third capacitor and thefifth switch.
 18. The circuit of claim 17, wherein the filtering circuitis adapted for connecting the node to the virtual ground only forfrequencies smaller than a threshold frequency greater than half theswitching frequency.
 19. The circuit of claim 18, wherein the filteringcircuit comprises an amplifier with differential inputs having an inputconnected to the node and having a main cut-off frequency, the thresholdfrequency of the filtering circuit corresponding to the main cut-offfrequency.
 20. The circuit of claim 17, wherein the filtering circuitcomprises at least one active filter comprising at least one activeelectronic component and at least one passive filter comprising at leastone passive electronic component.
 21. The circuit of claim 17, whereinthe capacitance of the second capacitor is smaller than the capacitanceof the first capacitor.
 22. The circuit of claim 17, wherein the groundterminal is connected to a source of a reference voltage and wherein theoperational amplifier comprises an additional input connected to saidsource of the reference voltage.
 23. The circuit of claim 17, furthercomprising a fifth switch across the second capacitor, the fifth switchbeing on, when the first and fourth switches are on, for a first timeperiod and off for a second time period.